DESIGN & IMPLEMENTATION OF FRACTIONAL – N FREQUENCY SYNTHESIZER (Journal of Engineering, 2006)
This research involves design & implementation of fractional – N frequency synthesizer with the following specifications: Frequency range (2350– 2750) MHz,Step size (1 kHz), Switching time 8.9 μs, & phase noise @10 kHz = -115dBc & spurious -69 dBc The third order Fractional –N technique was chosen to satisfy the design requirements. In this system the modulator placed on digital phase-locked loop to control the fractional value of thefrequency division ratio thereby eliminating spurious and allowing good phase noise performance. The development in I.C. technology provides the simplicity in the design of fractional –N frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar,modulator & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar, modulator & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The application of this synthesizer in frequency hopping systems, wireless transceivers ,GSM &radar because it has high switching speed ,low phase noise & low spurious level.